databend-cvbs
databend-cvbs · runs in vfpga-runnerModel
A composite-as-data circuit-bent VFPGA that databends the picture. A real 4-input bitwise LUT (the literal FPGA LUT16 truth table) mangles the picture's luma bit-planes into a bit-error field, a datapath bend byte-shifts / sample-drops / level-wraps the picture, and the two are XOR-combined (an absolute difference). p1 sweeps the LUT truth table (the XOR mask), p2 the byte-shift, p3 the sample-hold dropout density, p4 the level wrap-around. CIN1 adds onto the shift; GIN1 re-rolls the corruption seed. Every "random" bend is deterministic (frame + pixel + seed hashed) so it is reproducible.
I/O
- Video in: 1 (vin1…vin1)
- Video out: 1 (vout1)
Controls (param knobs)
| Slot | Knob | Range | Default | What it does |
|---|---|---|---|---|
p1 | xor-mask | 0 … 65535 | 27030 | The 16-bit LUT truth table (the XOR mask = 4-input parity a^b^c^d = 0x6996 by default). |
p2 | byte-shift | 0 … 0.5 | 0.04 | Horizontal sample (byte) shift — a smear offset. |
p3 | dropout | 0 … 1 | 0.15 | Per-column probability of a sample-hold dropout (frozen streaks). |
p4 | wrap | 0 … 1 | 0.2 | Level wrap-around: scaled luma past 1.0 wraps mod 1 (overflow glitch). |
CV roles
| Input | Role | What it modulates |
|---|---|---|
cv1 | SHIFT | Adds onto the byte-shift offset (patch an LFO/ramp to scan the smear). |
Each CV input has a bipolar SCALE attenuverter + OFFSET on the card, and an always-on scope.
Gate roles
| Input | Role | What it triggers |
|---|---|---|
g1 | RE-ROLL | A TRIGGER: each rising edge re-rolls the corruption seed → a fresh databend. |
Gate inputs raw-pass into the host's synthetic gN_evt params; the factory hysteresis edge-detects rising edges (rise > 0.6 / fall < 0.4).
Usage
Add a vfpga-runner, pick databend-cvbs from the card's load preset… menu, and patch the
active outputs into OUTPUT / a video mixer / a downstream effect.